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page 1 of 14 document no. doc-12314-2 www.psemi.com ?2013-2014 peregrine semiconductor corp. all rights reserved. pe42543 ultracmos ? sp4t rf switch 9 khz?18 ghz product specification features ?? harp technology-enhanced ?? fast settling time ?? no gate and phase lag ?? no drift in insertion loss and phase ?? fast switching time of 500 ns ?? low insertion loss ?? 1.20 db @ 3 ghz ?? 2.30 db @ 13.5 ghz ?? 2.70 db @ 16 ghz ?? 3.20 db @ 18 ghz ?? high isolation ?? 55 db @ 3 ghz ?? 32 db @ 13.5 ghz ?? 28 db @ 16 ghz ?? 25 db @ 18 ghz ?? esd performance ?? 2500v hbm on all pins ?? 150v mm on all pins ?? 250v cdm on all pins product description the pe42543 is a harp? technology-enhanced absorptive sp4t rf switch designed for use in test/ ate, microwave and other wireless applications. this broadband general purpose switch is a pin-compatible version of the pe42542 with faster switching time and settling time. it exhibits low insertion loss, high isolation and linearity performance from 9 khz through 18 ghz. no blocking capacitors are required if dc voltage is not present on the rf ports. the pe42543 is manufactured on peregrine?s ultracmos ? process, a patented variation of silicon-on- insulator (soi) technology on a sapphire substrate. peregrine?s harp technology enhancements deliver high linearity and excellent harmonics performance. it is an innovative feature of the ultracmos process, offering the performance of gaas with the economy and integration of conventional cmos . figure 1. functional diagram figure 2. package type 29-lead 4 ?? 4 mm lga doc-62642
product specification pe42543 page 2 of 14 document no. doc-12314-2 ultracmos ? rfic solutions ?2013-2014 peregrine semiconductor corp. all rights reserved. table 1. electrical specifications @ 25c (z s = z l = 50? ), unless otherwise noted normal mode 1 : v dd = 3.3v, v ss_ext = 0v or bypass mode 2 : v dd = 3.4v, v ss_ext = ?3.4v parameter path condition min typ max unit operating frequency 9 k 18 g hz insertion loss rfc?rfx 9 khz?10 mhz 10?3000 mhz 3000?7500 mhz 7500?10000 mhz 10000?13500 mhz 13500?16000 mhz 16000?18000 mhz 0.70 1.20 1.65 2.10 2.30 2.70 3.20 0.85 1.50 2.05 2.55 2.80 3.20 3.90 db db db db db db db isolation rfx?rfx 9 khz?10 mhz 10?3000 mhz 3000?7500 mhz 7500?10000 mhz 10000?13500 mhz 13500?16000 mhz 16000?18000 mhz 80 53 46 41 36 31 27 90 55 48 43 38 33 29 db db db db db db db isolation rfc?rfx 9 khz?10 mhz 10?3000 mhz 3000?7500 mhz 7500?10000 mhz 10000?13500 mhz 13500?16000 mhz 16000?18000 mhz 78 54 41 36 31 27 24 90 55 42 38 32 28 25 db db db db db db db return loss (active and common port) rfc?rfx 9 khz?10 mhz 10?3000 mhz 3000?18000 mhz 22 15 14 db db db return loss (terminated port ) rfx 9 khz?18000 mhz 14 db input 0.1db compression point 3 rfc?rfx fig. 4 dbm input ip2 rfc?rfx 10?18000 mhz 113 dbm input ip3 rfc?rfx 10?18000 mhz 59 dbm settling time 50% ctrl to 0.05 db final value 2 3 s switching time 50% ctrl to 90% or 10% of final value 500 800 ns notes: 1. normal mode: connect v ss_ext (pin 29) to gnd (v ss_ext = 0v) to enable internal negative voltage generator. 2. bypass mode: use v ss_ext (pin 29) to bypass and disable internal negative voltage generator. 3. the input 0.1db compression point is a linearity figure of merit. refer to table 3 for the rf input power p max (50 ? ).
product specification pe42543 page 3 of 14 document no. doc-12314-2 www.psemi.com ?2013-2014 peregrine semiconductor corp. all rights reserved. figure 3. pin configuration (top view) pin # pin name description 1, 3?6, 8?11, 13?16, 18?21, 23, 25, 26 gnd ground 2 rf2 1 rf port 2 7 rf4 1 rf port 4 12 rfc 1 rf common 17 rf3 1 rf port 3 22 rf1 1 rf port 1 24 v dd supply voltage (nominal 3.3v) 27 v2 digital control logic input 2 28 v1 digital control logic input 1 29 v ss_ext 2 external v ss negative voltage control pad gnd exposed pad: ground for proper operation table 2. pin descriptions notes: 1. rf pins 2, 7, 12, 17, and 22 must be at 0 vdc. the rf pins do not require dc blocking capacitors for proper operation if the 0 vdc requirement is met. 2. use v ss_ext (pin 29) to bypass and disable internal negative voltage generator. connect v ss_ext (pin 29) to gnd (v ss_ext = 0v) to enable internal negative voltage generator. table 3. operating ranges parameter symbol min typ max unit normal mode 1 (v ss_ext = 0v) supply voltage v dd 2.3 5.5 v supply current i dd 120 200 ua bypass mode 2 (v ss_ext = ?3.4v) supply voltage (v dd 3.4v for table 1 full spec. compliance) v dd 2.7 3.4 5.5 v supply current i dd 50 80 ua negative supply voltage v ss_ext ?3.6 ?3.2 v negative supply current i ss ?40 ?16 ua normal or bypass mode digital input high (v1, v2) v ih 1.17 3.6 v digital input low (v1, v2) v il ?0.3 0.6 v rf input power, cw (rfc?rfx) 3 9 khz?27.5 mhz 27.5 mhz?18 ghz p max,cw fig. 4 30 dbm dbm rf input power, pulsed (rfc?rfx) 4 9 khz?27.5 mhz 27.5 mhz?18 ghz p max,pulsed fig. 4 32 dbm dbm rf input power into terminated ports, cw (rfx) 3 9 khz?18.8 mhz 18.8 mhz?18 ghz p max,term fig. 4 20 dbm dbm operating temperature range t op ?40 +25 +85 c notes: 1. normal mode: connect v ss_ext (pin 29) to gnd (v ss_ext = 0v) to enable internal negative voltage generator 2. bypass mode: use v ss_ext (pin 29) to bypass and disable internal negative voltage generator 3. 100% duty cycle, all bands, 50 ? 4. pulsed, 5% duty cycle of 4620 s period, 50 ?
product specification pe42543 page 4 of 14 document no. doc-12314-2 ultracmos ? rfic solutions ?2013-2014 peregrine semiconductor corp. all rights reserved. exceeding absolute maximum ratings may cause permanent damage. operation should be restricted to the limits in the operating ranges table. operation between operating range maximum and absolute maximum for extended periods may reduce reliability. electrostatic discharge (esd) precautions when handling this ultracmos device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the rating specified. latch-up avoidance unlike conventional cmos devices, ultracmos devices are immune to latch-up. switching frequency the pe42543 has a maximum 25 khz switching rate when the internal negative voltage generator is used (pin 29 = gnd). switching frequency describes the time duration between switching events. switching time is the duration between the point the control signal reaches 50% of the final value and the point the output signal reaches within 10% or 90% of its target value. table 5. truth table state v1 v2 rf1 on 0 0 rf2 on 1 0 rf3 on 0 1 rf4 on 1 1 moisture sensitivity level the moisture sensitivity level rating for the pe42543 in the 29-lead 4 ?? 4 mm lga package is msl3. optional external v ss control (v ss_ext ) for proper operation, the v ss_ext control pin must be grounded or tied to the v ss voltage specified in table 3 . when the v ss_ext control pin is grounded, fets in the switch are biased with an internal negative voltage generator. for applications that require the lowest possible spur performance, v ss_ext can be applied externally to bypass the internal negative voltage generator. table 4. absolute maximum ratings parameter/condition symbol min max unit supply voltage v dd ?0.3 5.5 v digital input voltage (v1, v2) v ctrl ?0.3 3.6 v rf input power, cw (rfc?rfx) 1 9 khz?27.5 mhz n 27.5 mhz?18 ghz p max,abs fig. 4 33 dbm dbm storage temperature range t st ?65 +150 c esd voltage hbm, 3 all pins v esd,hbm 2500 v esd voltage mm 4 , all pins v esd,mm 150 v esd voltage cdm 5 , all pins v esd,cdm 250 v rf input power, pulsed (rfc?rfx) 2 9 khz?27.5 mhz n 27.5 mhz?18 ghz p max,pulsed fig. 4 34 dbm dbm rf input power into terminated ports, cw (rfx) 1 9 khz?18.8 mhz n 18.8 mhz?18 ghz p max,term fig. 4 22 dbm dbm notes: 1. 100% duty cycle, all bands, 50 ? 2. pulsed, 5% duty cycle of 4620 s period, 50 ? 3. human body model (mil_std 883 method 3015) 4. machine model (jedec jesd22-a115) 5. charged device model (jedec jesd22-c101) spurious performance the typical spurious performance of the pe42543 is ?150 dbm when v ss_ext = 0v (pin 29 = gnd). if further improvement is desired, the internal negative voltage generator can be disabled by setting v ss_ext = ?3.4v. hot-switching capability the maximum hot switching capability of the pe42543 is 20 dbm from 18.8 mhz to 18 ghz. the maximum hot switching capability below 18.8 mhz does not exceed the maximum rf cw terminated power, see figure 4. hot switching occurs when rf power is applied while switching between rf ports.
product specification pe42543 page 5 of 14 document no. doc-12314-2 www.psemi.com ?2013-2014 peregrine semiconductor corp. all rights reserved. \ 5 0 5 10 15 20 25 30 35 input ? power ? (dbm) frequency ? (mhz) p0.1 ? db ? compression ? @? 85c ? ambient max. ? rf ? input ? power, ? pulsed ? ( ? 27.5 ? mhz, ? 85c ? ambient) max. ? rf ? input ? power, ? cw ? ( ? 27.5 ? mhz, ? 85c ? ambient) max. ? rf ? input ? power, ? cw ? & ? pulsed ? (< ? 27.5 ? mhz, ? 85c ? ambient) max. ? rf ? terminated ? power, ? cw ? @ ? 85c ? ambient \ 5 0 5 10 15 20 25 30 35 input ? power ? (dbm) frequency ? (mhz) p0.1 ? db ? compression ? @ ? 25c ? ambient max. ? rf ? input ? power, ? pulsed ? ( ? 26.0 ? mhz, ? 25c ? ambient) max. ? rf ? input ? power, ? cw ? ( ? 26.0 ? mhz, ? 25c ? ambient) max. ? rf ? input ? power, ? cw ? & ? pulsed ? (< ? 26.0 ? mhz, ? 25c ? ambient) max. ? rf ? terminated ? power, ? cw ? @ ? 25c ? ambient figure 4a. power de-rating curve for 9 khz?18 ghz @ 25c ambient (50 ? figure 4b. power de-rating curve for 9 khz?18 ghz @ 85c ambient (50 ?
product specification pe42543 page 6 of 14 document no. doc-12314-2 ultracmos ? rfic solutions ?2013-2014 peregrine semiconductor corp. all rights reserved. typical performance data @ 25c and v dd = 3.3v (z s = z l = 50? ), unless otherwise noted figure 5. insertion loss (rfc?rfx) figure 6. insertion loss vs. temp (rfc?rfx) figure 7. insertion loss vs. v dd (rfc?rfx)
product specification pe42543 page 7 of 14 document no. doc-12314-2 www.psemi.com ?2013-2014 peregrine semiconductor corp. all rights reserved. typical performance data @ 25c and v dd = 3.3v (z s = z l = 50? ), unless otherwise noted figure 10. active port return loss vs. temp figure 8. rfc port return loss vs. temp figure 9. rfc port return loss vs. v dd figure 11. active port return loss vs. v dd
product specification pe42543 page 8 of 14 document no. doc-12314-2 ultracmos ? rfic solutions ?2013-2014 peregrine semiconductor corp. all rights reserved. typical performance data @ 25c and v dd = 3.3v (z s = z l = 50? ), unless otherwise noted figure 12. terminated port return loss vs. temp figure 13. terminated port return loss vs. v dd
product specification pe42543 page 9 of 14 document no. doc-12314-2 www.psemi.com ?2013-2014 peregrine semiconductor corp. all rights reserved. typical performance data @ 25c and v dd = 3.3v (z s = z l = 50? ), unless otherwise noted figure 14. isolation vs. temp (rfx?rfx)* figure 15. isolation vs. v dd (rfx?rfx)* note: * rf1 adjacent to rf3 rf2 adjacent to rf4 rf1 and rf3 opposite to rf2 and rf4
product specification pe42543 page 10 of 14 document no. doc-12314-2 ultracmos ? rfic solutions ?2013-2014 peregrine semiconductor corp. all rights reserved. typical performance data @ 25c and v dd = 3.3v (z s = z l = 50? ), unless otherwise noted figure 16. isolation vs. temp (rfc?rfx, rf1 or rf2 active)* figure 17. isolation vs. v dd (rfc?rfx, rf1 or rf2 active)* figure 18. isolation vs. temp (rfc?rfx, rf3 or rf4 active)* figure 19. isolation vs. v dd (rfc?rfx, rf3 or rf4 active)* note: * rf1 adjacent to rf3 rf2 adjacent to rf4 rf1 and rf3 opposite to rf2 and rf4
product specification pe42543 page 11 of 14 document no. doc-12314-2 www.psemi.com ?2013-2014 peregrine semiconductor corp. all rights reserved. evaluation kit the sp4t switch evaluation board was designed to ease customer evaluation of peregrine?s pe42543. the rf common port is connected through a 50 ? transmission line via the sma connector, j1. rf1, rf2, rf3 and rf4 ports are connected through 50 ? transmission lines via sma connectors j4, j3, j2 and j5, respectively. a 50 ? through transmission line is available via sma connectors j6 and j7, which can be used to de-embed the loss of the pcb. j13 provides dc and digital inputs to the device. the board is constructed of a four metal layer material with a total thickness of 62 mils. the top rf layer is rogers 4360 material with a thickness of 32 mils and the ? r = 6.4. the middle layers provide ground for the transmission lines. the transmission lines were designed using a coplanar waveguide with ground plane model using a trace width of 18 mils, trace gaps of 7 mils and metal thickness of 2.1 mils. for the true performance of the pe42543 to be realized, the pcb should be designed in such a way that rf transmission lines and sensitive dc i/o traces are heavily isolated from one another. high frequency insertion loss and return loss can be further improved by external series inductive tuning traces in the customer application board layout. for example, to improve 12?18 ghz performance, use ~180 ph for rfx ports and ~50 ph for rfc port. vector de-embed is recommended to more accurately calculate the performance of the dut. refer to application note 39 ? vector de- embedding of the pe42542 and pe42543 sp4t rf switches? for additional information. the half thru line data file can be downloaded from peregrine?s website to facilitate the vector de- embedding. figure 20. evaluation board layout prt-09205
product specification pe42543 page 12 of 14 document no. doc-12314-2 ultracmos ? rfic solutions ?2013-2014 peregrine semiconductor corp. all rights reserved. figure 21. evaluation board schematic doc-12327 caution: contains parts and assemblies susceptible to damage by electrostatic discharge (esd). thru 50 ohm 50 ohm 50 ohm 50 ohm 50 ohm 50 ohm c3 dni c7 dni c4 dni 1 1 3 3 5 5 7 7 2 2 4 4 6 6 8 8 10 10 12 12 14 14 13 13 9 9 11 11 j13 c5 dni c6 dni r5 dni r8 0ohm j 1 j 3 j2 j4 j 5 j7 j6 r7 0ohm r6 dni r1 dni r2 dni r3 dni r4 dni 1 gnd 2 rf2 3 gnd 4 gnd 5 gnd 6 gnd 7 rf4 8 gnd 9 gnd 10 gnd 11 gnd 12 rfc 13 gnd 14 gnd 15 gnd 16 gnd 17 rf3 18 gnd 19 gnd 20 gnd 21 gnd 22 rf1 23 gnd 24 vdd 25 dgnd 26 tmgnd 27 v2 28 v1 29 vss 30 gnd 31 gnd 32 gnd 33 gnd u1 pe42543 vdd
product specification pe42543 page 13 of 14 document no. doc-12314-2 www.psemi.com ?2013-2014 peregrine semiconductor corp. all rights reserved. top view bottom view side view recommended land pattern a (2x) c seating plane b (2x) pin #1 corner 4.00 4.00 1.13 (x4) 1.13 (x4) 0.40 0.4684 0.4284 0.4646 0.4948 0.10 (x29) 0.4484 0.700.05 0.20 x45 chamfer 1.13 1.13 0.26x0.30 (x6) 0.33x0.34 (x18) 0.30x0.30 (x5) 0.40 3.80 3.80 0.24 (x4) 0.24 (x4) (x5) 0.4284 0.4684 0.4684 0.4484 note: - dimensions concerning pad pitch are all mirrored across the y-axis 0.910.10 0.4484 0.4484 0.4684 0.4284 0.4484 0.24 (x4) 0.24 (x4) 0.4284 0.4684 0.4684 0.4484 0.4484 0.4484 figure 22. package drawing 29-lead 4 ?? 4 mm lga doc-50743 figure 23. top marking specification 42543 yyww zzzzz doc-51207-2 = pin 1 designator yyww = date code, last two digits of assembly year and work week zzzzz = last five characters of the assembly lot code
product specification pe42543 page 14 of 14 document no. doc-12314-2 ultracmos ? rfic solutions ?2013-2014 peregrine semiconductor corp. all rights reserved. table 6. ordering information order code description package shipping method PE42543A-X pe42543 sp4t rf switch 29-lead 4 ? 4 mm lga 500 units / t&r ek42543-02 pe42543 evaluation ki t evaluation kit 1 / box advance information: the product is in a formative or design stage. the datasheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification: the datasheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification: the datasheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify custom ers of the intended changes by issuing a cnf (customer notification form). the information in this datasheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, ultracmos and utsi are registered trademarks and harp, multiswitch and dune are trademarks of peregrine semiconductor corp. peregr ine products are protected under one or more of the following u.s. patents: http://patents.psemi.com . sales contact and information for sales and contact information please visit www.psemi.com . figure 24. tape and reel drawing

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